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HS-82C55ARH
September 1995
Radiation Hardened CMOS Programmable Peripheral Interface
Pinout
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW
PA3 PA2 PA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 PA4 39 PA5 38 PA6 37 PA7 36 WR 35 RESET 34 D0 33 D1 32 D2 31 D3 30 D4 29 D5 28 D6 27 D7 26 VDD 25 PB7 24 PB6 23 PB5 22 PB4 21 PB3
Features
* Radiation Hardened - Total Dose >105 RAD (Si) - Transient Upset <108 RAD (Si)/s - Latch Up Free EPI-CMOS * Low Power Consumption - IDDSB = 20A * Pin Compatible with NMOS 8255A and the Intersil 82C55A * High Speed, No "Wait State" Operation with 5MHz HS-80C86RH * 24 Programmable I/O Pins * Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors * Direct Bit Set/Reset Capability * Enhanced Control Word Read Capability * Hardened Field, Self-Aligned, Junction Isolated CMOS Process * Single 5V Supply * 2.0mA Drive Capability on All I/O Port Outputs * Military Temperature Range: -55oC to +125oC
PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2
Description
The Intersil HS-82C55ARH is a high performance, radiation hardened CMOS version of the industry standard 8255A and is manufactured using a hardened field, self-aligned silicongate CMOS process. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which are organized into two 8-bit and two 4-bit ports. Each port may be programmed to function as either an input or an output. Additionally, one of the 8-bit ports may be programmed for bi-directional operation,and the two 4-bit ports can be programmed to provide handshaking capabilities. The high performance, radiation hardness, and industry standard configuration of the HS-82C55ARH make it compatible with the HS-80C86RH radiation hardened microprocessor. Static CMOS circuit design insures low operating power. Bus hold circuitry eliminates the need for pull-up resistors. The Intersil hardened field CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power.
Pin Description
PIN D7 - D0 RESET CS RD WR DESCRIPTION Data Bus (Bi-Directional Reset Input Chip Select Read Input Write Input Port Address Port A (Bit) Port B (Bit) Port C (Bit) +5 volts DB NA 0 volts
Ordering Information
PART NUMBER HS1-82C55ARH-Q HS1-82C55ARH-8 HS1-82C55ARH/Sample TEMPERATURE -55oC to +125oC -55oC to +125oC +25oC PACKAGE 40 Lead SBDIP 40 Lead SBDIP
A0 - A1 PA7 - PA0 PB& - PB0 PC7 - PC0 VDD 40 Lead SBDIP GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
970
518060 3191.1
HS-82C55ARH Pin Description
SYMBOL PA0-7 PB0-7 PC0-3 PC4-7 D0-7 VDD GND CS RD PIN NUMBERS 1-4, 37-40 18-25 14-17 10-13 27-34 26 7 6 5 TYPE I/O I/O I/O I/O I/O I I I I DESCRIPTION Port A: General purpose I/O Port. Data direction and mode is determined by the contents of the Control Word. Port B: General purpose I/O port. See Port A. Port C (Lower): Combination I/O port and control port associated with Port B. See Port A. Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A. Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are low and as an output when CS and RD are low. VDD: The +5V power supply pin. A 0.1F capacitor between pins 26 and 7 is recommended for decoupling. Ground. Chip Select: A "low" on this input pin enables the communication between the HS-82C55ARH and the CPU. Read: A "low" on this input pin enables the HS-82C55ARH to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the HS-82C55ARH. Write: A "low" on this input pin enables the CPU to write data or control words into the HS-82C55ARH. Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the Least Significant Bits of the address bus (A0 and A1). Reset: A "high" on this input clears the control register and all ports (A, B, C) are set to the input mode. "Bus hold" devices internal to the HS-82C55ARH will hold the I/O port inputs to a logic "1" state with a maximum hold current of 400A.
WR A0 and A1
36 8, 9
I I
Reset
35
I
Functional Diagram
POWER SUPPLIES +5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA7 - PA0
BIDIRECTIONAL DATA BUS D7 - D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4)
I/O PC7 - PC4
GROUP B PORT C LOWER (4)
I/O PC3 - PC0
RD WR A1 A0 RESET
READ/WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
I/O PB7 - PB0
CS
Spec Number 971
518060
Specifications HS-82C55ARH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 40oC/W 6oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER TTL Output High Voltage SYMBOL VOH1 CONDITIONS VDD = 4.5V, IO = -2.5mA, VIN = 0V, 4.5V VDD = 4.5V, IO = -100A, VIN = 0V, 4.5V VDD = 4.5V, IO = 2.5mA, VIN = 0V, 4.5V VDD = 5.5V, VIN = 0V, 5.5V GROUP A SUBGROUP 1, 2, 3 TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC MIN 3.0 MAX UNITS V
CMOS Output High Voltage Output Low Voltage
VOH2
1, 2, 3
VDD0.4 -
-
V
VOL
1, 2, 3
0.4
V
Input Leakage Current
IIL or IIH
1, 2, 3
-1.0
1.0
A A A
Output Leakage Current
IOZL or IOZH IBHH
VDD = 5.5V, VIN = 0V, 5.5V
1, 2, 3
-10
10
Input Current Bus Hold High
VDD = 4.5V or 5.5V, VIN = 3.0V (See Note 1) Ports A, B, C VDD = 4.5V or 5.5V, VIN = 1.0V (See Note 2) Port A VDD = 5.5V, IO = 0mA, VIN =GND or VDD VDD = 4.5V, IO = -2.0mA, VIN = GND or VDD VDD = 4.5V and 5.5V, VIN = GND or VDD, f = 1MHz VDD = 5.5V, VIN = GND or VDD - 1.5V and VDD = 4.5V, VIN = 0.8V or VDD
1, 2, 3
-800
-60
Input Current Bus Hold Low
IBHL
1, 2, 3
-55oC, +25oC, +125oC
60
800
A
Standby Power Supply Current Darlington Drive Voltage
IDDSB
1, 2, 3
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
-
20
A
VDAR
1, 2, 3
3.9
-
V
Functional Tests
FT
7, 8A, 8B
-
-
-
Noise Immunity Functional Test (Note 4)
FN
7, 8A, 8B
-55oC, +25oC, +125oC
-
-
-
NOTES: 1. IBHH should be measured after raising VIN and then lowering to 3.0V. 2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V. 3. No internal current limiting exists on the Port Outputs. A resistor must be added externally to limit the current. 4. For VIH (VDD = 5.5V) and VIL (VDD = 4.5V) each of the following groups is tested separately with all other inputs using VIH = 2.6V, VIL = 0.4V: PA, PB, PC, Control Pins (Pins 5, 6, 8, 9, 35, 36).
Spec Number 972
518060
Specifications HS-82C55ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TA = -55oC to +125oC LIMITS PARAMETER READ Address Stable Before RD Address Stable After RD RD Pulse Width Data Valid From RD Data Float After RD Time Between RDs and/ or WRs WRITE Address Stable Before WR Address Stable After WR TAVWL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC 0 ns TAVRL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC 0 ns SYMBOL CONDITIONS SUBGROUPS TEMPERATURE MIN MAX UNITS
TRHAX TRLRH TRLDV TRHDX TRWHRWL
VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
0 250 10 300
200 -
ns ns ns ns ns
TWHAX
VDD = 4.5, 5.5V, Ports A and B VDD = 4.5, 5.5V, Port C
9, 10, 11
-55oC, +25oC, +125oC
20
-
ns
9, 10, 11
-55oC, +25oC, +125oC
100
-
ns
WR Pulse Width Data Valid to WR High Data Valid After WR High
TWLWH TDVWH TWHDX
VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V, Ports A and B VDD = 4.5, 5.5V, Port C
9, 10, 11 9, 10, 11 9, 10, 11
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
100 100 30
-
ns ns ns
9, 10, 11
-55oC, +25oC, +125oC
100
-
OTHER TIMINGS WR = 1 to Output Peripheral Data Before RD Peripheral Data After RD ACK Pulse Width STB Pulse Width Peripheral Data Before STB High Peripheral Data After STB High ACK = 0 to Output ACK = 1 to output Float TWHPV TPVRL VDD = 4.5, 5.5V VDD = 4.5, 5.5V 9, 10, 11 9, 10, 11 -55oC, +25oC, +125oC -55oC, +25oC, +125oC 0 350 ns ns
TRHPX TKLKH TSLSH TPVSH
VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
0 200 100 20
-
ns ns ns ns
TSHPX
VDD = 4.5, 5.5V
9, 10, 11
-55oC, +25oC, +125oC
50
-
ns
TKLPV TKHPZ
VDD = 4.5, 5.5V VDD = 4.5, 5.5V
9, 10, 11 9, 10, 11
-55oC, +25oC, +125oC -55oC, +25oC, +125oC
10
175 -
ns ns
Spec Number 973
518060
Specifications HS-82C55ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TA = -55oC to +125oC (Continued) LIMITS PARAMETER WR = 1 to OBF = 0 ACK = 0 to OBF = 1 STB = 0 to IBF = 1 RD = 1 to IBF = 0 RD = 0 to INTR = 1 STB = 1 t INTR = 1 ACK = 1 to INTR = 1 WR = 0 to INTR = 0 RESET Pulse Width SYMBOL TWHOL TKLOH TSLIH TRHIL TRLNL TSHNH TKHNH TWLNL TRSHRSL CONDITIONS VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V VDD = 4.5, 5.5V (Note 2) SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC MIN 500 MAX 150 150 150 150 200 150 150 200 UNITS ns ns ns ns ns ns ns ns ns
NOTES: 1. AC's tested at worst case VDD, guaranteed over full operating range. 2. Period of initial RESET pulse after power-on must be at least 50s. Subsequenct RESET pulses may be 500ns minimum.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VDD = Open, f = 1MHz, All measurements referenced to device ground VDD = Open, f = 1MHz, All measurements referenced to device ground VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V TEMPERATURE TA = +25oC MIN MAX 10 UNITS pF
I/O Capacitance
CI/O
TA = +25oC
-
20
pF
Data Float After RD ACK = 1 to Output Float
TRHDX TKHPZ
-55oC < TA < +125oC -55oC < TA < +125oC
-
75 250
ns ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics
TALBE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS See +25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7, 9)
Spec Number 974
518060
Specifications HS-82C55ARH
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Static Current Input Leakage Current Output Leakage Current Low Level Output Voltage TTL Output High Voltage CMOS Output High Voltage SYMBOL IDDSB IIL, IIH IOZL, IOZH VOL VOH1 VOH2 DELTA LIMITS 10A 200nA 2A 80mV 600mV 150mV
TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A (Note 1) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 RECORDED FOR -Q 1 (Note 2) 1, (Note 2) RECORDED FOR -8
TESTED FOR -Q 1, 7, 9 1, 7, 9, 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11
TESTED FOR -8 1, 7, 9 1, 7, 9 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 1, 7, 9
Subgroup B5 Subgroup B6 Group C
Sample 5005 Sample 5005 Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, 1, 7, 9 N/A
1, 2, 3, (Note 2) N/A
Group D Group E, Subgroup 2 NOTES:
Sample 5005 Sample 5005
1, 7, 9 1, 7, 9
-
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only
Spec Number 975
518060
HS-82C55ARH Intersil Space Level Product Flow -Q
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A CSI and/or GSI PreCap (Note 6) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125oC Min, Method 1015
NOTES: 1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group B Samples, Group D Test and Group D Samples. 5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 6. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection. 7. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * Group B and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 1) 100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 2(T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 2) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 3) Sample - Group B, Method 5005 (Note 4) Sample - Group D, Method 5005 (Notes 4 and 5) 100% Data Package Generation (Note 7) CSI and/or GSI Final (Note 6)
Spec Number 976
518060
HS-82C55ARH Intersil Space Level Product Flow -8
GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B CSI an/or GSI PreCap (Note 5) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% External Visual 100% Initial Electrical Test
NOTES: 1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 5. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection. 6. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Group B, C and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 2) Sample - Group B, Method 5005 (Note 3) Sample - Group C, Method 5005 (Notes 3 and 4) Sample - Group D, Method 5005 (Notes 3 and 4) 100% Data Package Generation (Note 6) CSI and/or GSI Final (Note 5)
AC Test Circuit
V1
AC Testing Input, Output Waveforms
INPUT R1 2.8V
FROM OUTPUT UNDER TEST R2 C1*
TEST POINT
1.5V 0.4V
1.5V
* Includes stray and jig capacitance TEST CONDITIONS DEFINITION TABLE V1 1.7V R1 523 R2 Open C1 150pF
NOTE: AC Testing: All parameters tested as per test circuits. Input rise and fall times are driven at 1V/ns.
Spec Number 977
518060
HS-82C55ARH Waveforms
TRLRH RD TPVRL INPUT TAVRL CS, A1, A0 TRHAX CS, A1, A0 TRHPX D7 - D0 TAVWL TWHAX WR TDVWH TWHDX TWLWH
D7 - D0 TRLDV TRHDZ
OUTPUT TWHPV
FIGURE 1. MODE 0 (BASIC INPUT)
FIGURE 2. MODE 0 (BASIC OUTPUT)
TSLSH STB WR
TWHOL
TKLOH IBF TSLIH TRHIL INTR TSHNH RD TSHPX INPUT FROM PERIPHERAL TPVSH OUTPUT TWHPV ACK TKLKH TKHNH INTR TWLNL TRLNL OBF
FIGURE 3. MODE 1 (STROBED INPUT)
FIGURE 4. MODE 1 (STROBED OUTPUT)
DATA FROM CPU TO HS-82C55ARH WR TKLOH OBF TWHOL INTR ACK TSLSH STB IBF TSLIH TKLPV TPVSH PERIPHERAL BUS RD DATA FROM PERIPHERAL TO HS-82C55ARH TKHPX A0 - A1, CS TAVRL TSHPX DATA FROM HS-82C55ARH TO PERIPHERAL TRLRH TRHIL RD TRHDX DATA FROM HS-82C55ARH TO CPU TAVRL DATA BUS HIGH IMPEDANCE VALID HIGH IMPEDANCE TRHAX TKLKH DATA BUS TDVWH TWHDX WR TWLWH A0 - A1, CS TAVWL TWHAX
FIGURE 6. WRITE TIMING
FIGURE 5. MODE 2 (BIDIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
FIGURE 7. READ TIMING
Spec Number 978
518060
HS-82C55ARH Burn-In Circuits
PROGRAMMABLE PERIPHERAL INTERFACE
VDD
PROGRAMMABLE PERIPHERAL INTERFACE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 F4 F0 F5 F0 F2 F1 F0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD F7 F3 F4 F6 F5 F0
STATIC CONFIGURATION NOTES: 1. VDD = 6.0V 0. 5% 2. IDD <500A 3. TA Min = +125oC NOTES:
DYNAMIC CONFIGURATION 1. VDD = 6.0V 5% for Burn-In 2. VDD = 5.0V 5% for Life Test 3. All resistors are 10K 5% 4. -0.3V VIL 0.8V 5. VDD - 1.0V VIH VDD 6. IDD < 5mA 7. F0 = 10KHz, 50% Duty cycle 8. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 . . . F7 = F6/2 9. TA Min = +125oC
Spec Number 979
518060
HS-82C55ARH Irradiation Circuit
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
1 2 3 4 5 6 7 8 +5.5V 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 +5.5V
NOTE: 1. VDD = 5.5V
Spec Number 980
518060
HS-82C55ARH Functional Description
The HS-82C55ARH is a programmable peripheral interface designed to allow microcomputer systems to control and interface with all types of peripheral devices.It has the ability to generate and respond to all asynchronous handshaking signals necessary to transfer data to and from peripheral devices, and it can also interrupt the processor when a peripheral needs servicing. These capabilities allow the HS-82C55ARH to be used in an unlimited number of applications including EXTERNAL SYSTEM CONTROL, ASYNCHRONOUS DATA TRANSFER, and SYSTEMS MONITORING.
Ports A, B, C
The HS-82C55ARH contains three 8-bit ports (A, B and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the HS-82C55ARH. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus hold devices are present on Port A. See Figure 9A. One 8-bit data input/output latch/buffer and one 8bit data input buffer. See Figure 9B. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs in conjunction with Ports A and B. See Figure 9B.
Port B Port C
Data Bus Buffer
This tri-state bidirectional 8-bit buffer is used to interface the HS-82C55ARH to the system data bus (see Figure 8). Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.
MASTER RESET
POWER SUPPLIES +5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA 7PA0
RD CONTROL
BIDIRECTIONAL DATA BUS D7D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)
I/O PC 7PC4
INTERNAL DATA IN INTERNAL DATA OUT WR SIGNAL
EXTERNAL PORT A PIN
I/O PC3PC0
(A)
I/O PB 7PB0
RD WR A1 A0 RESET CS
READ/ WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
VDD MASTER RESET P
FIGURE 8. BLOCK DIAGRAM DATA BUS BUFFER, READ/WRITE, GROUP A AND B CONTROL LOGIC FUNCTIONS
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfer of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.
INTERNAL DATA IN INTERNAL DATA OUT WR SIGNAL
EXTERNAL PORT B, C PIN
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU writes a control word to the HS-82C55ARH. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the HS-82C55ARH. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control Logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Control Group - Port A and Port C upper (C7 - C4) Control Group - Port B and Port C lower (C3 - C0).
(B) FIGURE 9. I/O PORT CONFIGURATION
Operational Description
Control Word
The data direction and mode of Ports A, B and C are determined by the contents of the Control Word. See Figure 11. The Control Word can be both written and read as shown in Table 1 and 2. During write operations, the function of the Control Word being written is determined by data bit D7. If D7 is low, the data on D0 - D3 will set or reset one of the bits of Port C. See Figure 12. During read Operations, the Spec Number
518060
981
HS-82C55ARH
Control Word will always be in the format illustrated in Figure 11 with Bit D7 high to indicate Control Word Mode Information.
ADDRESS BUS CONTROL BUS DATA BUS CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT RD, WR MODE 0 B D7 - D0 C A0 - A1 CS A PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1
TABLE 3. A1 X X A0 X X RD X 1 WR X 1 CS 1 0 DISABLE FUNCTION Data Bus - 3-State Data Bus - 3-State
8 I/O
4 I/O
4 I/O
8 I/O GROUP A
PB7 - PB0 PC3 - PC0 PC7 - PC4 PA7 - PA0
PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2
MODE 1
B
C
A
8 I/O
8 I/O
PB7 - PB0 CONTROL CONTROL PA7 - PA0 OR I/O OR I/O
MODE 2
B
C
A
MODE SET FLAG 1 = ACTIVE
FIGURE 11. MODE SET CONTROL WORD FORMAT
8 I/O PB7 - PB0 I/O 8 BIDIRECTIONAL
Mode Selection
There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the RESET input goes "high", all ports will be set to the input mode with all 24 port lines held at the logic "one" level by internal bus hold devices. After reset, the HS82C55ARH can remain in the input mode with no additional initialization required. This eliminates the need for pullup or pulldown resistors in all CMOS designs. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single HS-82C55ARH to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status register, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape recorder on an interrupt-driven basis. Spec Number 982
CONTROL
PA7 - PA0
FIGURE 10. BASIC MODE DEFINITIONS & BUS INTERFACE TABLE 1. INPUT OPERATION (READ) Port A - Data Bus Port B - Data Bus Port C - Data Bus Control Word - Data Bus
A1 0 0 1 1
A0 0 1 0 1
RD 0 0 0 0
WR 1 1 1 1
CS 0 0 0 0
TABLE 2. OUTPUT OPERATION (WRITE) Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus - Control Word
A1 0 0 1 1
A0 0 1 0 1
RD 1 1 1 1
WR 0 0 0 0
CS 0 0 0 0
518060
HS-82C55ARH
The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the HS-82C55ARH has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins.
CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Control Functions
When the HS-82C55ARH is programmed to operate in Mode 1 or Mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from Port C, can be inhibited or enable by setting or resetting the associated INTE flip-flop, using the Bit Set/Reset function of Port C. This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. INTE Flip-Flop Definition: (BIT-SET) - INTE is SET - Interrupt enable. (BIT-RESET) - INTE is RESET - Interrupt disable. NOTE: All mask flip-flops are automatically reset during mode selection and device Reset.
X
X
X
BIT SET/RESET 1 = SET 0 = RESET BIT SELECT 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 B0 1 B1 1 B2
DON'T CARE
Operating Modes
Mode 0 (Basic Input/Output)
This functional configuration provides simple input and output operations for each of the three ports. No handshaking it required, data is simply written to or read from a specific port. Mode 0 Basic Functional Definitions: * Two 8-bit ports and two 4-bit ports * Any port can be input or output * Outputs are latched * Inputs are not latched * 16 different Input/Output configurations possible
BIT SET/RESET FLAG 0 = ACTIVE
FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT
Single Bit/Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. See Figure 12. This feature reduces software requirements in control-based applications.
TRLRH RD TPVRL INPUT TAVRL CS, A1, A0 TRHAX TRHPX
D7 - D0 TRLDV TRHDX
FIGURE 13. MODE 0 (BASIC INPUT)
TWLWH WR TWHDX TDVWH D7 - D0 TAVWL CS, A1, A0 TWHAX
OUTPUT TWHPV
FIGURE 14. MODE 0 (BASIC OUTPUT)
Spec Number 983
518060
HS-82C55ARH Mode 0 Port Definition
A D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PORT A Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input GROUP A PORT C (UPPER) Output Output Output Output Input Input Input Input Output Output Output Output Input Input Input Input NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PORT B Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input GROUP B PORT C (LOWER) Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input
Mode 0 Configurations
CONTROL WORD #0
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
CONTROL WORD #1
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #3
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
Spec Number 984
518060
HS-82C55ARH Mode 0 Configurations
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
(Continued) CONTROL WORD #5
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
CONTROL WORD #4
B
CONTROL WORD #6
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #7
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #9
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
CONTROL WORD #10
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
Spec Number 985
518060
HS-82C55ARH Mode 0 Configurations
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
(Continued) CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
CONTROL WORD #12
B
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
Operating Modes
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or "handshaking" signals. In Mode 1, Port A and Port B use the lines on Port C to generate or accept these "handshaking" signals. Mode 1 Basic Functional Definitions: * Two Groups (Group A and Group B) * Each group contains one 8-bit port and one 4-bit control/ data port. * The 8-bit data port can be either input or output. Both inputs and outputs are latched. * The 4-bit port is used for control and status of the 8-bit port.
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the rising edge of STB and reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port.
INTE A
Controlled by Bit Set/Reset of PC4.
INTE B
Controlled by Bit Set/Reset of PC2.
MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1
PC6, 7 1 = INPUT 0 = OUTPUT PA7 - PA0 8 STB A IBF A RD PC3 2 PC6, 7 I/O INTR A PC0 INTR B PB7 - PB0 INTE B PC2 PC1 8 STB B IBF B
Input Control Signal Definition
STB (Strobe Input)
A "low" on this input loads data into the input latch.
INTE A PC4 PC5
IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input.
RD
FIGURE 15. MODE 1 INPUT
Spec Number 986
518060
HS-82C55ARH
TSLSH STB
INTE A
Controlled by Bit Set/Reset of PC6.
IBF TSLIH
INTE B
TRLNL TRHIL
Controlled by Bit Set/Reset of PC2.
TWHOL WR
INTR TSHNH RD TSHPX INPUT FROM PERIPHERAL TPVSH INTR TWLNL ACK OBF
TKHOL
FIGURE 16. MODE 1 (STROBED INPUT)
Output Control Signal Definition
OBF (Output Buffer Full F/F)
The OBF output will go "low" to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF. See Note 1. The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low.
TKLKH TKHNH OUTPUT TWHPV
FIGURE 18. MODE 1 (STROBED OUTPUT) NOTE: 1. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generate an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF.
ACK (Acknowledge Input)
A "low" on this input informs the HS-82C55ARH that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data. See Note 1.
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
PORT A (STROBED INPUT) PORT B (STROBED OUTPUT) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 0 PORT A (STROBED OUTPUT) PORT B (STROBED INPUT) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 1 1
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set by the rising edge of ACK and reset by the falling edge of WR.
MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 0
PC6, 7 1 = INPUT 0 = OUTPUT PA7 - PA0 PC4 PC5
PC4, 5 1 = INPUT 0 = OUTPUT PA7 - PA0 PC7 PC6 PC3 2 I/O 8 OBF B ACK B INTR B RD PC4, 5 PB7 - PB0 PC2 PC1 PC0 8 STB B IBF B INTR B I/O
RD
8 STB A IBF A INTR A 2
WR
8 OBF A ACK A INTR A
PC4, 5 1 = INPUT 0 = OUTPUT PA7 - PA0 PC7 INTE A WR PC3 2 PC4, 5 I/O INTR A PC6 8 OBF A ACK A WR PC0 INTR B PB7 - PB0 PC1 INTE B PC2 8 OBF B ACK B
PC3 PC6, 7 WR PB7 - PB0 PC1 PC2 PC0
FIGURE 17. MODE 1 OUTPUT
FIGURE 19. COMBINATIONS OF MODE 1
Spec Number 987
518060
HS-82C55ARH Operating Modes
MODE 2 (Strobed Bidirectional Bus I/O)
The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). "Handshaking" signals are provided to maintain proper bus flow discipline similar to MODE 1. Interrupt generation and enable/disable functions are also available. Mode 2 Basic Functional Definitions: * Used in Group A only. * One 8-bit, bidirectional bus port (Port A) and a 5-bit control port (Port C). * Both inputs and outputs are latched. * The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A).
PC3 INTR A 1 0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1/0 1/0 1/0 PC2 - PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT GROUP B MODE 0 = MODE 0 1 = MODE 1
FIGURE 20. MODE CONTROL WORD
PA7- PA0
8 OBF A ACK A
Bidirectional Bus I/O Control Signal Definition INTR (Interrupt Request)
A high on this output can be used to interrupt the CPU for both input or output operations. INTR will be set either by the rising edge of ACK (INTE1 = 1) or the rising edge of STB (INTE2 = 1). INTR will be reset by the falling edge of WR (if previously set by the rising edge or ACK), the falling edge of RD (if previously set by the rising edge of STB), or the falling edge of WR when immediately following a low RD pulse or the falling edge of RD when immediately following a low WR pulse (if previously set by the rising edges of both ACK and STB).
INTE 1
PC7 PC6
INTE 2 WR RD
PC7 PC6
STB A IBF A
3 PC2- PC0 I/O
FIGURE 21. MODE 2 (BIDIRECTIONAL)
Output Operations OBF (Output Buffer Full)
The OBF output will go "low" to indicate that the CPU has written data out to Port A.
WR TKHOL OBF TWHOL INTR ACK TSLSH STB IBF TSLIH TKLPV TPVSH PERIPHERAL BUS RD DATA FROM PERIPHERAL TO HS-82C55ARH TKHPX TKLKH DATA FROM CPU TO HS-82C55ARH
ACK (Acknowledge)
A "low" on this input enables the tri-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high impedance state.
INTE 1 (The INTE Flip-Flop Associated with OBF)
Controlled by Bit Set/Reset of PC6.
Input Operations STB (Strobe Input)
A "low" on this input loads data into the input latch.
TSHPX DATA FROM HS-82C55ARH TO PERIPHERAL
TRHIL
IBF (Input Buffer Full F/F)
A "high" on this output indicates that data has been loaded into the input latch.
DATA FROM HS-82C55ARH TO CPU
INTE 2 (The INTE Flip-Flop Associated with IBF)
Controlled by Bit Set/Reset of PC4.
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. FIGURE 22. MODE 2 (BIDIRECTIONAL)
Spec Number 988
518060
HS-82C55ARH
MODE DEFINITION SUMMARY MODE 0 IN PA0 AP1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In In In In In In In In In In In In In In In In In OUT Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out IN In In In In In In In In In In In In In In In In INTR B IBF B STB B INTR A STB A IBF A I/O I/O MODE 1 OUT Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out INTR B OBF B ACK B INTR A I/O I/O ACK A OBF A I/O I/O I/O INTR A STB A IBF A ACK A OBF A MODE 2 GROUP A ONLY
Mode 0 or Mode 1 Only
Special Mode Combination Considerations
There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a "Set Mode" command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 25. Through a "Write Port C" command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a "Write Port C" command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to change an interrupt enable flag, the "Set/Reset Port C Bit" command must be used. With a "Set/Reset Port C Bit" command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C fare not affected by a "Set/ Reset Port C Bit" command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the "Set/ Reset Port C Bit" command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 25.
D7 I/O D6 I/O D5
INPUT CONFIGURATION D4 INTEA D3 INTRA D2 INTEB D1 IBFB D0 INTRB
IBFA
GROUP A OUTPUT CONFIGURATION D7 OBFA D6 INTEA D5 I/O D4 I/O D3 INTRA D2 INTEB
GROUP B
D1 OBFB GROUP B
D0 INTRB
GROUP A
FIGURE 23. MODE 1 STATUS WORD FORMAT
D7 OBFA
D6 INTE1
D5 IBFA GROUP A
D4 INTE2
D3 INTRA
D2 X
D1 X GROUP B
D0 X
NOTE: (Defined by Mode 0 or Mode 1 Selection) FIGURE 24. MODE 2 STATUS WORD FORMAT
Spec Number 989
518060
HS-82C55ARH
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function.
INTERRUPT ENABLE FLAG* INTE B INTE A2 INTE A1 POSITION PC2 PC4 PC6 ALTERNATE PORT C PIN SIGNAL (MODE) ACKB (Output Mode 1) or STBB (Input Mode 1) STBA (Input Mode 1 or Mode 2) ACKA (Output Mode 1 or Mode 2)
Reading Port C Status (Figures 23 and 24)
In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes 1 or 2, Port C generates or accepts "hand shaking" signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly.
FIGURE 25. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
Spec Number 990
518060
HS-82C55ARH Metallization Topology
DIE DIMENSIONS: 3420m x 4350m x 485m 25m METALLIZATION: Type: Al/Si Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 7.7 x 104 A/cm2
Metallization Mask Layout
HS-82C55ARH
(15) PC1 (14) PC0 (13) PC4 (12) PC5 (10) PC7 (11) PC6
(7) VSS
PC2 (16) PC3 (17) PB0 (18) PB1 (19) PB2 (20)
(6) CS
(9) A0
(8) A1
(5) RD (4) PA0 (3) PA1 (2) PA2 (1) PA3
PB3 (21) PB4 (22) PB5 (23) PB6 (24) PB7 (25)
(40) PA4 (39) PA5 (38) PA6 (37) PA7 (36) WR
RESET (35)
VDD (26)
D7 (27)
D6 (28)
D5 (29)
D4 (30)
D3 (31)
D2 (32)
D1 (33)
D0 (34)
Spec Number 991
518060
HS-82C55ARH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 992

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